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           - Training Calendar - Jan 2015
           - Training Calendar - Feb 2015
            - Training Calendar - Mar 2015
Services / Corporate Training / Mar 2015
 

Altera FPGA Public Training Calendar - Mar 2015 (Bangalore)

Course Name Curriculum Duration Date Prerequisite Price
Introduction to the Altera DSP Builder and Simulink
  • DSP Builder and Simulink
  • DSP Builder overview
  • MATLAB and Simulink basics
  • DSP Builder library block set highlights
  • Model guidelines and procedures
  • DSP standard block set - Rate Change
  • Blocks, Mega Core Functions, and Interface blocks.
  • RTL Generation, RTL functional
  • Verification(HIL), Integration
  • Exercises
1 Day 16 Mar 15 Altera FPGA Architecture, working knowledge with Altera Quartus II and basic FPGA based project implementation experience, DSP basics Registration Open
Applications of Altera DSP Builder in Video and Image Processing
  • DSP Builder in Video and Image Processing
  • Introduction to Video processing suite
  • Developing the simple edge detection design in Simulink flow
  • Simulation using HIL through Simulink
  • Using signal tap for verification
  • Developing the simple edge detection design in QuartusII flow
  • Verification on board through QuartusII flow
  • Comparison of the results
1 Day 17 Mar 15 Altera FPGA Architecture, working knowledge with Altera Quartus II and basic FPGA based project implementation experience, DSP, DSP builder and Simulink basics Registration Open
Applications of Altera DSP Builder in Communication and signal processing
  • DSP Builder in Communication and signal processing
    • Introduction to Communication suite
    • Developing two-channel DSB demodulator in Matlab / Simulink
    • Verifying the demodulator in simulation
    • Architecture exploration
    • Design optimization - trade-offs
    • WiMAX Digital Up converter - theory
  • Exercises
1 Day 18 Mar 15 Altera FPGA Architecture, working knowledge with Altera Quartus II and basic FPGA based project implementation experience, DSP, DSP builder and Simulink basics Registration Open
Introduction to Altera ARM-SOC FPGA Design
  • SOC Overview, HPS introduction
  • Multi Processor Unit (MPU) subsystem overview
  • Hardware design flow
  • Software flow overview
  • Make overview
  • ARM DS-5 Altera Edition overview
  • Lab Exercise
  • Creating an ARM Based SoC System Using Qsys
  • Bare-metal HWlibs Exercise
1 Day 20 Mar 15 Basic Digital Electronics Design, Altera FPGA Architecture, working knowledge with Altera Quartus II and basic FPGA based project implementation experience Basics of processor/controller based design Registration Open
Altera ARM-SOC FPGA Design - Hardware
  • Hard Processor System (HPS) Overview
    • SOC Overview, HPS introduction
    • Multi Processor Unit (MPU) subsystem overview
    • System management peripherals
    • Memory Interfaces, Interconnects, Peripherals, DMA Controller
    • Hardware design
    • Hardware design flow
    • Software handoff
    • Avalon/AXI overview, Configuring the HPS IP, HPS simulation
    • HPS configuration and booting, HW debug
    • Lab Exercise
    • Creating an ARM Based SoC System Using Qsys
    • Accessing FPGA from System Console tool
    • Read Register in HPS from FPGA
    • FPGA peripheral accessing from HPS
    • Cross trigger Signal Tap from HPS
  • Exercises
2.5 Day 23 Mar 15 to 25 Mar 15 Basic Digital Electronics Design, Altera FPGA Architecture, working knowledge with Altera Quartus II and basic FPGA based project implementation experience Basics of processor/controller based design Registration Open
Altera ARM-SOC FPGA Design - Software
  • Software design flow
    • Software flow overview
    • Make overview
    • ARM DS-5 Altera Edition overview
  • Boot flow
  • HPS flash programmer overview
  • PreLoader overview
    • Preloader introduction
    • Preloader tools, Preloader flow
    • Preloader GUI, Preloader CLI
    • User Boot loader
  • Hardware libraries (HWLibs) overview
  • Hardware/software file handoff
  • Operating system support
    • RTOS Overview, Linux, Yocto project
  • Building Linux
    • Getting the Source Code
    • Setup Tool chain
    • Build Filesystem
    • Build u-boot, Build Linux
    • Creating SD-Card Image
  • Device tree overview
    • Device Tree Introduction
    • Device Tree Generator
    • Compile Device Tree
  • Software debug
    • Altera SOC Debug Architecture
    • Cortex A-9 Debug
    • Real Time Trace, Cross Triggering
    • Debugger Configuration
  • Lab Exercise
    • Preloader Exercise
    • Bare-metal HWlibs Exercise
    • Booting Linux and Blink LED Exercise
    • Cross Triggering and Debug Exercise
2.5 days 25 Mar 15 to 27 Mar 15 The Quartus II Software Design Series: Foundation Hard Processor System (HPS) Overview Registration Open

Note: Service tax 12.36% would be additional applicable on above trainings.

Please feel free to write to training@dexceldesigns.com for more information or call us at +91-998-605-2742

 
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