SPI is a full duplex, serial bus that is very common in the embedded
world. SPI devices are normally smaller in size, compared to parallel
interface devices, mainly because of its lesser I/O count. With this
IP, the user can interface a PC that has a UART port, to communicate to
SPI slave devices.
This IP can communicate up to seven SPI slaves with the help of UART
interface. The internal block diagram of the IP is given in the above
figure. CoreUART block handles the UART side communication.
In the current design, we are making use of Actel’s UART core. This can
be replaced with any other UART core. The SPI Master block handles the
SPI side communication. The UART to SPI control logic helps the
interconnection between these two interfaces.
This interface communicates with the SPI Slave devices using the
signals - serial data out port (MOSI), serial data in port (MISO),
output clock (SCLK), and slave select ports (SS_N [7:0]).
The IP can fit in any application where an SPI device has to be used.
Typical applications includes interfacing of EEPROM , Flash memories,
Sensors etc. "Can be targetted for other FPGAs of customer's choice.".
- Design RTL code
- Archived Project files
- Test benches
- User manual